1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof.
2. Description of Related Art
Static Random Access Memory (SRAM) devices contain flip-flop memory cells. SRAM essentially works on the principle of a switch. An advantage of SRAM devices is that they do not require a refresh clock; the data is maintained by the switches so long as power is supplied. But SRAM devices need a lot of transistors for the memory cells (typically 2-4 transistors per bit), and therefore, they are relatively expensive and provide for a relatively low density of integration. By contrast, Dynamic Random Access Memory (DRAM) devices are relatively cheaper and have a simpler cell structure than SRAM devices (typically 1 transistor per bit). DRAM devices use capacitors to store charge. Due to leakage of the charge, DRAM cells require periodic refresh operations to maintain stored data.
A pseudo SRAM (PSRAM) device implements the operation of an SRAM device using DRAM cells. The PSRAM device can operate in a combined mode in which the PSRAM device operates in an asynchronous mode like an SRAM device and also operates in a synchronous mode like a DRAM device.
When a write command is generated in the asynchronous mode, a conventional PSRAM device stores an address and data input together with the write command in a register during a write command generation period and writes the data stored in the register to a corresponding memory cell during a subsequent write period in a late write operation. In addition, when a read command is generated in the asynchronous or synchronous mode, the conventional PSRAM reads data from a register not from a memory cell in a bypass operation when an address input together with the read command is the same as an address stored in the register.
However, conventional semiconductor memory devices, e.g., conventional PSRAM devices, using both of the synchronous mode and the asynchronous mode may have a data coherency problem when the synchronous mode is converted into the asynchronous mode or when the asynchronous mode is converted into the synchronous mode. For instance, when conversion between the synchronous mode and the asynchronous mode is performed, if an address which is input together with a late write command input in the asynchronous mode is the same as an address which is input together with a write command input in the synchronous mode, a data value may change, causing the data coherency problem.
Moreover, when conversion between the synchronous mode and the asynchronous mode is performed in the conventional PSRAM devices, it takes time to identify the asynchronous mode or the synchronous mode, which may generate a dummy cycle time.